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D at a S h eet , V 1. 0, A ug. 200 1
C167CS-xC, Step BA
16-Bit Single-Chip Microcontroller Bare Die Delivery
M i c r o c o n t ro l le r s
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Edition 2001-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D at a S h eet , V 1. 0, A ug. 200 1
C167CS-xC, Step BA
16-Bit Single-Chip Microcontroller Bare Die Delivery
M i c r o c o n t ro l le r s
Never
stop
thinking.
C167CS-xC Revision History: Previous Version: Page
(Bare Die Delivery) 2001-08 V1.0
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
16-Bit Single-Chip Microcontroller C166 Family C167CS-xC
C167CS-xC
* High Performance 16-bit CPU with 4-Stage Pipeline - 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock - 400/303 ns Multiplication (16 x 16 bit), 800/606 ns Division (32/16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 MBytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area * 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns * 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) * Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input * On-Chip Memory Modules - 3 KBytes On-Chip Internal RAM (IRAM) - 8 KBytes On-Chip Extension RAM (XRAM) - 32 KBytes On-Chip Program Mask ROM * On-Chip Peripheral Modules - 24-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 s - Two 16-Channel Capture/Compare Units - 4-Channel PWM Unit - Two Multi-Functional General Purpose Timer Units with 5 Timers - Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) - Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 x 15 Message Objects (Full CAN/Basic CAN), can work on one bus with 30 objects - On-Chip Real Time Clock * Up to 16 MBytes External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width - Five Programmable Chip-Select Signals - Hold- and Hold-Acknowledge Bus Arbitration Support * Idle, Sleep, and Power Down Modes with Flexible Power Management * Programmable Watchdog Timer and Oscillator Watchdog * Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
Data Sheet 1 V1.0, 2001-08
C167CS-xC Bare Die Step BA
* Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards * On-Chip Bootstrap Loader This document describes several derivatives of the C167 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 Type SAK-C167CS-4RC SAK-C167CS-LC SAL-C167CS-LC1) SAL-C167CS-L33C1)
1)
C167CS-xC Bare Die Derivative Synopsis Ordering Code Q67120D.... Q67120C2200 Q67120C2274 Q67120C2275 Program Memory 32 KByte ROM ------Operating Temperature -40 to +125 C -40 to +125 C -40 to +150 C -40 to +150 C Wafers Whole Sawn Sawn Sawn
The designation SAL-... conforms to the valid ProElectron specification. These devices were named SAA-... formerly.
Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. For simplicity all versions are referred to by the term C167CS-xC throughout this document.
Data Sheet
2
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Introduction The C167CS-xC derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 16.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM.
VAREF VAGND VDD
VSS
XTAL1 XTAL2 RSTIN RSTOUT NMI EA READY ALE RD WR/WRL Port 5 16 Bit
MCL04411
Port 0 16 Bit Port 1 16 Bit Port 2 16 Bit
C167CS-xC
Port 3 15 Bit Port 4 8 Bit Port 6 8 Bit Port 7 8 Bit Port 8 8 Bit
Figure 1
Logic Symbol
Data Sheet
3
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Pad Configuration (top view)
Pad 110
Pad 74
Pad 111
C167CS-xC
Pad 146
0.0 Pad 1 x 0.0 Position of Logo and Marking Pad 36
Figure 2 Several pins of Port 4 and Port 8 can have CAN interface lines assigned to them. Table 2 on the following pages lists the possible assignments.
Data Sheet
4
V1.0, 2001-08
Pad 37
y
Pad 73
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions
Symbol Pad In / Position [m] Function Num Out x y
9AREF 9AGND
P5.10 P5.11 P5.12 P5.13 P5.14 P5.15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O
305 460 615 770 925 1081 1236 1391 1563 1688 1960 2139 2318 2497 2676 2855 3034 3214
0 Reference voltage for the A/D converter. 0 Reference ground for the A/D converter. 0 Port 5 input, analog input AN10, external up/down T6EUD. 0 Port 5 input, analog input AN11, external up/down T5EUD. 0 Port 5 input, analog input AN12, timer input T6IN. 0 Port 5 input, analog input AN13, timer input T5IN. 0 Port 5 input, analog input AN14, external up/down T4EUD. 0 Port 5 input, analog input AN15, external up/down T2EUD. 0 Digital Ground. 0 Digital Supply Voltage. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC0IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC1IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC2IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC3IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC4IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC5IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC6IO. 0 Port 2 input/output (open drain, sp. threshold), Capture-Input/Compare-Output CC7IO.
9SS 9DD
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
Data Sheet
5
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y
9SS 9DD
P2.8
19 20 21
I/O
3393 3572 3751
0 Digital Ground. 0 Digital Supply Voltage. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC8IO, Fast Interrupt EX0IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC9IO, Fast Interrupt EX1IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC10IO, Fast Interrupt EX2IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC11IO, Fast Interrupt EX3IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC12IO, Fast Interrupt EX4IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC13IO, Fast Interrupt EX5IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC14IO, Fast Interrupt EX6IN. 0 Port 2 input/output (open drain, sp. threshold), Capt. Input/Comp. Output CC15IO, Fast Interrupt EX7IN, Timer T7 input T7IN. 0 Port 3 input/output (open drain, sp. threshold), Timer T0 Input T0IN. 0 Port 3 input/output (open drain, sp. threshold), Timer T6 Toggle Latch Output T6OUT. 0 Port 3 input/output (open drain, sp. threshold), CAPREL Capture Input CAPIN. 0 Port 3 input/output (open drain, sp. threshold), Timer T3 Toggle Latch Output T3OUT.
6 V1.0, 2001-08
P2.9
22
I/O
3930
P2.10
23
I/O
4109
P2.11
24
I/O
4288
P2.12
25
I/O
4467
P2.13
26
I/O
4646
P2.14
27
I/O
4826
P2.15
28
I/O
5005
P3.0 P3.1 P3.2 P3.3
29 30 31 32
I/O I/O I/O I/O
5184 5363 5542 5721
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P3.4 P3.5 33 34 35 36 37 38 39 40 41 42 43 44 P3.13 P3.15 45 46 47 I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O I/O I/O I/O I/O 5900 6079 6258 6437 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 0 Port 3 input/output (open drain, sp. threshold), Timer T3 ext.up/down T3EUD. 0 Port 3 input/output (open drain, sp. threshold), Timer T4 Input T4IN. 0 Digital Ground. 0 Digital Supply Voltage. 498 Port 3 input/output (open drain, sp. threshold), Timer T3 Input T3IN. 695 Port 3 input/output (open drain, sp. threshold), Timer T2 Input T2IN. 892 Port 3 input/output (open drain, sp. threshold), SSC Master-Rec./Slave-Transmit I/O MRST. 1090 Port 3 input/output (open drain, sp. threshold), SSC Master-Transmit/Slave-Rec. O/I MTSR. 1287 Port 3 input/output (open drain, sp. threshold), ASC0 Clock/Data Output (Asyn./Syn.) TxD0. 1484 Port 3 input/output (open drain, sp. threshold), ASC0 Data Input (Asyn.) or I/O (Syn.) RxD0. 1681 Port 3 input/output (open drain, sp. threshold). 1878 High Byte Enable BHE, High Byte Write Strobe WRH. 2075 Port 3 input/output (open drain, sp. threshold), SSC Master(Slave) Clock Output(Input) SCLK. 2272 Port 3 input/output (open drain, sp. threshold). 2469 System Clock Output (=CPU Clock) CLKOUT, Programmable Frequency Output FOUT. 2666 Digital Supply Voltage. 2837 Digital Ground. 2993 Port 4 input/output, Segment Address Line A16. 3149 Port 4 input/output, Segment Address Line A17. 3306 Port 4 input/output, Segment Address Line A18. 3462 Port 4 input/output, Segment Address Line A19.
7 V1.0, 2001-08
9SS 9DD
P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12
9DD 9SS
P4.0 P4.1 P4.2 P4.3
48 49 50 51 52 53
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P4.4 P4.5 P4.6 54 55 56 I/O I/O I/O 6936 6936 6936 3618 Port 4 input/output, Segment Address Line A20, CAN2 Receive Data Input CAN2_RxD. 3775 Port 4 input/output, Segment Address Line A21, CAN1 Receive Data Input CAN1_RxD. 3931 Port 4 input/output, Segment Address Line A22 CAN1 Transmit Data Output CAN1_TxD CAN2 Transmit Data Output CAN2_TxD. 4087 Port 4 input/output, Segment Address Line A23, CAN1 Receive Data Input CAN1_RxD CAN2 Transmit Data Output CAN2_TxD, CAN2 Receive Data Input CAN2_RxD. 4244 Digital Supply Voltage. 4400 Digital Ground. 4556 External Memory Read Strobe RD. 4712 External Memory Write(Low) Strobe WR (WRL). 4869 Ready Input. 5025 Address Latch Enable Output. 5181 External Access Enable pin. 5338 PORT0 input/output, Address/Data Line AD0. 5494 PORT0 input/output, Address/Data Line AD1. 5650 PORT0 input/output, Address/Data Line AD2. 5807 PORT0 input/output, Address/Data Line AD3. 5963 PORT0 input/output, Address/Data Line AD4. 6119 PORT0 input/output, Address/Data Line AD5. 6275 PORT0 input/output, Address/Data Line AD6. 6432 PORT0 input/output, Address/Data Line AD7. 6588 PORT0 input/output, Address/Data Line AD8. 7086 Digital Supply Voltage. 7086 Digital Ground. 7086 PORT0 input/output, Address/Data Line AD9. 7086 PORT0 input/output, Address/Data Line AD10.
8 V1.0, 2001-08
P4.7
57
I/O
6936
9DD 9SS
RD WR(L) ALE EA P0L.0 P0L.1 P0L.2 P0L.3 P0L.4 P0L.5 P0L.6 P0L.7 P0H.0
58 59 60 61 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
O O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6936 6437 6274 6110 5947
READY 62
9DD 9SS
P0H.1 P0H.2
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P0H.3 P0H.4 P0H.5 P0H.6 P0H.7 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 78 79 80 81 82 83 84 85 86 87 88 89 90 91 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I 5783 5620 5456 5293 5129 4966 4802 4639 4475 4312 4148 3985 3821 3658 3494 7086 PORT0 input/output, Address/Data Line AD11. 7086 PORT0 input/output, Address/Data Line AD12. 7086 PORT0 input/output, Address/Data Line AD13. 7086 PORT0 input/output, Address/Data Line AD14. 7086 PORT0 input/output, Address/Data Line AD15. 7086 PORT1 input/output, Address Line A0, analog input AN16. 7086 PORT1 input/output, Address Line A1, analog input AN17. 7086 PORT1 input/output, Address Line A2, analog input AN18. 7086 PORT1 input/output, Address Line A3, analog input AN19. 7086 PORT1 input/output, Address Line A4, analog input AN20. 7086 PORT1 input/output, Address Line A5, analog input AN21. 7086 PORT1 input/output, Address Line A6, analog input AN22. 7086 PORT1 input/output, Address Line A7, analog input AN23. 7086 Digital Supply Voltage. 7086 Must be connected to 9DD.1) Standard oscillator mode, single-chip reset with PORT0-configuration. 7086 Digital Ground. 7086 PORT1 input/output, Address Line A8. 7086 PORT1 input/output, Address Line A9. 7086 PORT1 input/output, Address Line A10. 7086 PORT1 input/output, Address Line A11. 7086 PORT1 input/output, Addr. Line A12, Capt. Input/Comp. Output CC24.
9 V1.0, 2001-08
9DD
C167CS 92 MODE
9SS
P1H.0 P1H.1 P1H.2 P1H.3 P1H.4
93 94 95 96 97 98
I/O I/O I/O I/O I/O
3331 3167 3004 2840 2677 2513
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P1H.5 P1H.6 P1H.7 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 I/O I/O I/O O I I/O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O 2350 2186 2023 1859 1708 1479 1316 1152 989 825 662 498 0 0 0 0 0 0 0 0 0 7086 PORT1 input/output, Addr. Line A13, Capt. Input/Comp. Output CC25. 7086 PORT1 input/output, Addr. Line A14, Capt. Input/Comp. Output CC26. 7086 PORT1 input/output, Addr. Line A15, Capt. Input/Comp. Output CC27. 7086 Digital Supply Voltage. 7086 Output of the oscillator amplifier circuit. 7086 Input to oscillator amplifier and internal clock generator. 7086 Digital Ground. 7086 Reset Input with Schmitt-Trigger characteristics, output in bidirectional reset mode. 7086 Internal Reset Indication Output. 7086 Non-Maskable Interrupt Input. 7086 Digital Ground. 7086 Digital Supply Voltage. 6588 Port 6 input/output, Chip Select 0 Output CS0. 6404 Port 6 input/output, Chip Select 1 Output CS1. 6220 Port 6 input/output, Chip Select 2 Output CS2. 6036 Port 6 input/output, Chip Select 3 Output CS3. 5852 Port 6 input/output, Chip Select 4 Output CS4. 5668 Port 6 input/output, External Hold Request Input HOLD. 5485 Port 6 input/output, External Hold Acknowledge Output HLDA. 5301 Port 6 input/output, Bus Request Output BREQ. 5117 Port 8 input/output, Capt.-Input/Comp.-Output CC16IO, CAN1 Receive Data Input CAN1_RxD, CAN2 Receive Data Input CAN2_RxD.
10 V1.0, 2001-08
9DD
XTAL2 XTAL1
9SS
RSTIN RST OUT NMI
9SS 9DD
P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P8.0
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P8.1 120 I/O 0 4933 Port 8 input/output, Capt.-Input/Comp.-Output CC17IO, CAN1 Transmit Data Output CAN1_TxD, CAN2 Transmit Data Output CAN2_TxD. 4749 Port 8 input/output, Capt.-Input/Comp.-Output CC18IO, CAN1 Receive Data Input CAN1_RxD, CAN2 Receive Data Input CAN2_RxD. 4565 Port 8 input/output, Capt.-Input/Comp.-Output CC19IO, CAN1 Transmit Data Output CAN1_TxD, CAN2 Transmit Data Output CAN2_TxD. 4381 Port 8 input/output, Capt.-Input/Comp.-Output CC20IO. 4197 Port 8 input/output, Capt.-Input/Comp.-Output CC21IO. 4013 Port 8 input/output, Capt.-Input/Comp.-Output CC22IO. 3829 Port 8 input/output, Capt.-Input/Comp.-Output CC23IO. 3646 Digital Supply Voltage. 3462 Digital Ground. 3278 Port 7 input/output, (open drain, sp. threshold), PWM Channel Output POUT0. 3094 Port 7 input/output, (open drain, sp. threshold), PWM Channel Output POUT1. 2910 Port 7 input/output, (open drain, sp. threshold), PWM Channel Output POUT2. 2726 Port 7 input/output, (open drain, sp. threshold), PWM Channel Output POUT3. 2542 Port 7 input/output, (open drain, sp. threshold), Capt.-Input/Comp.-Output CC28IO. 2358 Port 7 input/output, (open drain, sp. threshold), Capt.-Input/Comp.-Output CC29IO.
11 V1.0, 2001-08
P8.2
121
I/O
0
P8.3
122
I/O
0
P8.4 P8.5 P8.6 P8.7
123 124 125 126 127 128 129 130 131 132 133 134
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 0 0 0 0 0 0 0 0 0 0 0
9DD 9SS
P7.0 P7.1 P7.2 P7.3 P7.4 P7.5
Data Sheet
C167CS-xC Bare Die Step BA
Table 2
Pad Definitions and Functions (cont'd)
Symbol Pad In / Position [m] Function Num Out x y P7.6 P7.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9
1)
135 136 137 138 139 140 141 142 143 144 145 146
I/O I/O I I I I I I I I I I
0 0 0 0 0 0 0 0 0 0 0 0
2174 Port 7 input/output, (open drain, sp. threshold), Capt.-Input/Comp.-Output CC30IO. 1990 Port 7 input/output, (open drain, sp. threshold), Capt.-Input/Comp.-Output CC31IO. 1701 Port 5 input, analog input AN0. 1546 Port 5 input, analog input AN1. 1391 Port 5 input, analog input AN2. 1236 Port 5 input, analog input AN3. 1081 Port 5 input, analog input AN4. 925 Port 5 input, analog input AN5. 770 Port 5 input, analog input AN6. 615 Port 5 input, analog input AN7. 460 Port 5 input, analog input AN8. 305 Port 5 input, analog input AN9.
Prepared to enable Enhanced Mode, i.e. low-power oscillator mode, single-chip reset with RD/ALEconfiguration.
Note: All 9SS pads and all 9DD pads must be connected to the system ground and the power supply, respectively. The pad definitions and locations in this table are only valid for the indicated device and design step.
Data Sheet
12
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Handling Of Unconnected Pads Signal input stages may generate undesired switching noise and cross-current when left open. Respect the following precautions for unconnected (not bonded) pads: Table 3 Pad Type Power Supply Standard IO pads Input port pads Double-bond ports Configuration lines Required control lines Optional control lines
1) 2) 3)
Precautions for Unconnected Pads Recommended Action Always connect! Switch to output Disable input stages via P5DIDIS Related Pads
9DD, 9SS, 9AREF, 9AGND
PORT0, PORT11), P2, P3, P4, P6, P7, P8 P5
P3.12 (43/44), P3.15 (46/47) Connect port pad (43, 46), if the alternate output (44, 47) is used.2) Always connect! Always connect! Can be left open EA, C167CSMODE, RD3) XTAL1, RSTIN, NMI RD3), WR(L), READY, ALE, RSTOUT
The lower part of PORT1 (P1L) may be left open and its input stages can then be disabled via P1DIDIS. Port pad is input in this case! If the port pad is used, the corresponding alternate output pad may be left open. Pin RD can be used for configuration to disable the OWD. Otherwise it is held high by an internal pullup.
Data Sheet
13
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Functional Description As the standard packaged devices are made from this silicon the C167CS-xC dies provide exactly the same functionality and behaviour. Also the DC characteristics and AC characteristics are compatible with those of the packaged devices. For a description of the functionality and the DC and AC parameters please refer to the following documents (or later versions thereof): * C167CS-4R/-L Data Sheet, Version 2.2, 2001-08 * C167CS Derivatives User's Manual, Version 2.0, 2000-07
Data
Dual Port
ProgMem
ROM 32 KByte
32
Instr. / Data
C166-Core
16
IRAM
Internal RAM 3 KByte
CPU
16 Data
16
XRAM
6+2 KByte
External Instr. / Data
Osc / PLL
PEC
XTAL
Interrupt Controller 16-Level Priority 16
On-Chip XBUS (16-Bit Demux)
RTC
WDT
CAN2
Rev 2.0B active
Interrupt Bus 16
Peripheral Data Bus
CAN1
Rev 2.0B active
ADC
10-Bit 16+8 Channels
ASC0
(USART)
SSC
(SPI)
GPT
T2 T3 T4 T5
PWM CCOM2 CCOM1
T7 T8 T0 T1
Port 4
8
EBC
XBUS Control External Bus Control
Port 0 16 Port 1 16
Port 6
8
BRGen Port 5 16
BRGen Port 3 15
T6 Port 7 8 Port 8 8
MCB04323_7CS
Figure 3
Block Diagram
Data Sheet
14
V1.0, 2001-08
Port 2
16
C167CS-xC Bare Die Step BA
Absolute Maximum Ratings Table 4 Parameter Storage temperature Junction temperature Voltage on 9DD pins with respect to ground (9SS) Voltage on any pin with respect to ground (9SS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Absolute Maximum Rating Parameters Symbol Limit Values min. max. 150 150 6.5 C C V under bias -65 -40 -0.5 -0.5 -10 Unit Notes
7ST 7J 9DD 9IN
9DD + 0.5 V
10 |100| mA mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (9IN > 9DD or 9IN < 9SS) the voltage on 9DD pins with respect to ground (9SS) must not exceed the values defined by the absolute maximum ratings.
Storage Conditions The C167CS-xC dies may be stored for a certain time under the conditions described below. Table 5 Packing Vacuum pack Bare Die Storage Conditions and Duration Environment Air Temperature 15 ... 30 C Rel. Humidity < 60 % Storage Time < 4 Months
Data Sheet
15
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C167CS-xC. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 6 Parameter Digital supply voltage Operating Condition Parameters Symbol Limit Values min. max. 5.5 5.5 0 -40 -40 5 50 50 150 125 V V V mA mA pF C C Active mode, ICPUmax = 33 MHz PowerDown mode Reference voltage Per pin 2)
3) 3)
Unit Notes
9DD
4.5 2.5 1)
Digital ground voltage Overload current Absolute sum of overload currents External Load Capacitance Temperature of the bottom side of the die
1) 2)
9SS ,OV
|,OV|
&L 7D
Pin drivers in fast edge mode 4) SAL-C167CS-xC... SAK-C167CS-xC...
Output voltages and output currents will be reduced when 9DD leaves the range defined for active mode. Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. 9OV ! 9DD+0.5V or 9OV 9SS-0.5V). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR, etc. Not 100% tested, guaranteed by design and characterization. The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in dynamic current mode must be respected when designing the system.
3) 4)
Data Sheet
16
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Chip Outline
0.38
7.29
y
x 0,0 0.090 0.125 min Typical Dimensions in mm
Figure 4
Data Sheet 17 V1.0, 2001-08
0.090
7.44
C167CS-xC Bare Die Step BA
Table 7 Item
Wafer Characteristics Characteristic 262 (geometrically) 2 AlCu Met1: 450 nm, Met2: 800 nm Ti SOG-CMP AlSiCu (Al 98.5% - SI 1% - Cu 0.5%) Oxide (300 nm) + nitride (500 nm) None (silicon) 1.0 - 1.3 typical
Chips per wafer Metallization layers Metallization material Metallization thickness Metallization barrier material Metallization isolation Metallization material on pads Passivation Backside metallization1) Inkdot diameter
1)
The backside of the chip can either be left unconnected or must be connected to VSS.
The wafers are glued to a plastic tape which is fixed within a plastic ring (see Figure 5). Wafers can be shipped in one piece or sawn into individual dies. Note: Please refer also to the document "Bare Die Packing Information".
Data Sheet
18
V1.0, 2001-08
C167CS-xC Bare Die Step BA
Wafer Outline
Plastic Frame Plastic Tape Wafer
152.4 (6") 210 230 Dimensions in mm Figure 5
Data Sheet
19
V1.0, 2001-08
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